The emergence of data-intensive applications in mobile environments (e.g., smart phones, tablet personal computers, and the like) has resulted in portable electronic systems with increasingly large dynamic memories (e.g., dynamic random access memory (DRAM)). A typical operating pattern exhibited by these applications involves relatively short bursts of operations followed by comparatively longer standby periods. Due to refresh requirements and peripheral circuit leakage, DRAM consumes substantial power even during standby and thus has a significant impact on battery life of such portable electronic systems.
More particularly, due to charge leakage, data stored in a DRAM cell must be periodically refreshed. The elapsed time from when data is written to a DRAM cell to when the data is on the threshold of becoming corrupted due to charge leakage is referred to as the data retention time of the memory. The longer the data retention time, the less frequently the memory cell needs to be refreshed. Each refresh operation in a DRAM consumes power. Therefore, the longer the data retention time, the lower the required refresh power. It is important to keep in mind that, not only do the memory cells leak, but also the DRAM peripheral circuits leak continually. The power consumed through peripheral circuit leakage may dwarf that consumed by refresh, particularly in the case of embedded DRAM—a high performance DRAM technology.
Refresh (or data retention) and peripheral circuit leakage power is consumed even when the memory is not being accessed (i.e., when the memory is in a standby mode). Standby mode is often defined as a mode in which the memory is not being accessed (e.g., during a read or write operation), and some or all of the data stored in the memory is retained. In a power critical application, often the majority of the power is consumed in standby. In such an application, it is important to minimize both peripheral circuit leakage and refresh power to as low a level as possible.